Article ID: 117389 - View products that this article applies to.
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The following chart lists the exceptions that can be generated by the Intel 80286, 80386, 80486, and Pentium processors:
Exception | Description (dec/hex) | ----------|------------------------------------------------- 0 00h | Divide error: | Occurs during a DIV or an IDIV instruction when the | divisor is zero or a quotient overflow occurs. 1 01h | Single-step/debug exception: | Occurs for any of a number of conditions: | - Instruction address breakpoint fault | - Data address breakpoint trap | - General detect fault | - Single-step trap | - Task-switch breakpoint trap 2 02h | Nonmaskable interrupt: | Occurs because of a nonmaskable hardware interrupt. 3 03h | Breakpoint: | Occurs when the processor encounters an INT 3 instruction. 4 04h | Overflow: | Occurs when the processor encounters an INTO instruction | and the OF (overflow) flag is set. 5 05h | Bounds check (BOUND instruction): | Occurs when the processor, while executing a BOUND | instruction, finds that the operand exceeds the specified | limit. 6 06h | Invalid opcode: | Occurs when an invalid opcode is detected. 7 07h | Coprocessor not available: | Occurs for one of two conditions: | - The processor encounters an ESC (escape) instruction | and the EM (emulate) bit of CR0 (control register zero) | is set. | - The processor encounters either the WAIT instruction or | an ESC instruction and both the MP (monitor | coprocessor) and TS (task switched) bits of CR0 are set. 8 08h | Double fault: | Occurs when the processor detects an exception while | trying to invoke the handler for a prior exception. 9 09h | Coprocessor segment overrun: | Occurs when a page or segment violation is detected while | transferring the middle portion of a coprocessor operand | to the NPX. 10 0Ah | Invalid TSS: | Occurs if, during a task switch, the new TSS is invalid. 11 0Bh | Segment not present: | Occurs when the processor detects that the present bit of | a descriptor is zero. 12 0Ch | Stack exception: | Occurs for one of two conditions: | - As a result of a limit violation in any operation that | refers to SS (stack segment register) | - When attempting to load SS with a descriptor that is | marked as not-present but is otherwise valid 13 0Dh | General protection violation: | Each protection violation that does not cause another | exception causes a general protection exception. | - Exceeding segment limit when using CS, DS, ES, FS, or GS | - Exceeding segment limit when referencing a descriptor | table | - Transferring control to a segment that is not executable | - Writing to a read-only data segment or a code segment | - Reading from an execute-only segment | - Loading SS with a read-only descriptor | - Loading SS, DS, ES, FS, or GS with a descriptor of a system | segment | - Loading DS, ES, FS, or GS with the descriptor of an | executable segment that is also not readable | - Loading SS with the descriptor of an executable segment | - Accessing memory through DS, ES, FS, or GS when the segment | register contains a NULL selector | - Switching to a busy task | - Violating privilege rules | - Loading CR0 with PG=1 and PE=0 | - Interrupt or exception through trap or interrupt gate from | V86 mode to a privilege level other than 0 14 0Eh | Page fault: | Occurs when paging is enabled (PG=1) and the processor | detects one of the following conditions while translating | a linear address to a physical address: | - The page-directory or page-table entry needed for the | address translation has 0 in its present bit. | - The current procedure does not have sufficient privilege | to access the indicated page. 15 0Fh | (Reserved) 16 10h | Coprocessor error: | Occurs when the processor detects a signal from the | coprocessor on the ERROR# input pin. 17 11h | (Reserved) through | 31 1Fh |
"Intel 80386 Programmer's Reference Manual,"
Article ID: 117389 - Last Review: October 14, 2003 - Revision: 1.1
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